Employee History

The list below outlines a handful of the designs that our engineers have completed prior to the inception of L&D Physical Design

Transparent Mux

8 million gates
5 hierarchical blocks
200 MHz core
800 MHz interface blocks (timing closure within magma, verified in Spice)
Utilized clock gating & clock gapping circuits

Enhanced FEC

6 million gates
5 hierarchical blocks
155 MHz core
800 MHz interface blocks (timing closure within magma, verified in Spice)
Utilized clock gating & clock gapping circuits

Aggregator

4 million gates
1 hierarchical block
155 / 250 MHz core
3G SerDes interface
Inclusive clock gating circuits

10G to XGMII

Flat design, 400K gates
155 MHz core
400 MHz interface
10G SerDes interface
Inclusive clock gating & clock gapping circuits

XAUI to 10G

Flat design, 350K gates
155 MHz core
400 MHz interface
10G and 3G SerDes interfaces
Inclusive clock gating & clock gapping circuits